High speed latches are in general important components of today's wireless transceivers utilizing digital radio and in particular essential in pulse generation and duty cycle control in telecommunications' applications.
An example of a high speed latch is disclosed in an article by Behzad Razavi et al., “Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS”, IEEE journal of solid-state circuits, vol. 30, No. 2, February 1995.
A high frequency divider circuit is disclosed in WO2011/003101A1. This 50% duty cycle frequency divider utilizes a pair of latches, which uses a multi-bit digital controller for setting a variable resistance element. This variable resistance element provides a variable load and enables the reduction of the output resistance at higher frequencies.
The latches in WO2011/003101A1 have a major drawback, i.e. the operation functionality of the circuit depends on the output signal swing. That is to say, Vgs of the uppermost PMOS devices is determined by the output signal swing. Hence successive reduction of the output load seen by the circuit at higher frequencies could be perhaps a remedy to progressive shrinking of the signal swing with frequency.